In a cross-point memory architecture read operation, a voltage differential is applied between a row and a column of a memory cell in the memory. The logic state of the cell is then determined by measuring a bias voltage and determining whether the bias voltage exceeds a cell threshold voltage.
During this conventional read operation, it is possible that a relatively large capacitive discharge may occur through the memory that is capable of disturbing (e.g., corrupting) the logic state of the cell and/or significantly reducing the number of read operations that can be performed on the cell before the cell's data will need to be rewritten. As can be appreciated, this may significantly degrade the memory's performance and/or increase the complexity of the operations and/or circuitry involved in managing the memory.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly.